Annunciator system



Oct. 15, 1963 J. J. MNElLL 3,107,348

ANNUNCIATOR SYSTEM Filed Jan. 2, 1958 4 Sheets-Sheet 2 Lll Annunciutor I200' I43 'v-cf Dc Annunciotor I52 0c (N'MIGI H?- ORI58 M57 7 DC g 4.Flasher N59 ORIGS I ES-rd msv F l'g.5.

WITNESSES: 'NVENTOR 59, g Q I Jon J McNel K 74 x0. WA W W ATTOB/NEY Oct.15, 1963 J. MONEILL, 3,107,348

ANNUNCIATOR SYSTEM Filed Jan. 2, 1958 4 Sheets-Sheet 5 Oct. 15, 1963 J.J. MONEILL 3,107,348

ANNUNCIATOR SYSTEM Filed Jan. 2, 1958 4 Sheets-Sheet 4 SN N8 Na I 08 mm2% vvm mw QW MH QN \i hmm QVN M EN 8% 08 ohm EN ow 3% mm w United StatesPatent 3,107,343 ANNUNCIATOR SYSTEM Jon 1!. McNeill, Pittsburgh, Pa,assignor to Westinghouse Electric Corporation, East Pittsburgh, Pin, acorporation of Pennsylvania Filed .lan. 2, 1958, Ser. No. 706,687@iaiins. (El. 346-213) This invention relates to annunciator systems ofa type which embodies static logic elements, such for example assaturable core or other static switching devices, to perform the variousannunciator functions.

An object of this invention is to provide an annunciator having staticlogic elements which cooperate with a flasher to produce a flashinglight for indicating an abnormal condition in a monitored circuit.

Another object of this invention is to provide an annunciator havingstatic elements which cooperate with a pulse producing device to providea pulsing signal for indicating an abnormal condition at a monitoredpoint.

It is a further object of this invention to provide an annunciatorhaving static elements cooperating to actuate a first indicator oralarm, and cooperating with a pulse producing device to actuate a secondindicator of a different type.

It is a further object of this invention to provide an annunciatorhaving saturable core or other static logic elements cooperating toactuate an audio signal and to flash or cause other changes in theillumination of a light I for indicating an abnormal condition in amonitored circuit.

Still another object of this invention is to provide an annunciatorsystem having saturable core static logic elements which respond to anabnormal condition in a monitored circuit to actuate an audio indicatorand a flashing visual indicator, and which thereafter responds to anacknowledge signal to deactuate the audio indicator and simultaneouslyswitch the flashing visual indicator to a steady visual indicator.

Another object of this invention is to provide an annuuciator systemhaving saturable core static logic elements which cooperate withimpedance means to actuate a dim light indicator in response to normalconditions at a monitored point and to actuate a flashing or brightlight indicator in response to an abnormal condition at the monitoredpoint.

An additional object of the invention is to make possible the use of alow energy output flasher of the static type, by connecting the flasherat the input side of the amplifiers which feed the lamps, so that theflasher does not have to handle the power for lighting the lamps.

Other objects of the invention will in part be obvious and will in partappear hereinafter.

The invention, accordingly, comprises the features of construction,combination of elements, and arrangements of parts which will beexemplified in the constructions hereinafter set forth and illustratedin the drawings.

For a fuller understanding of the nature and objects of the inventionreference should be had to the following detailed description taken inconnection with the accompanying drawings, in which:

FIGURE 1 is a schematic diagram of interconnected static elementsillustrating a basic embodiment of this invention;

FIG. 2 is a schematic diagram of a transformer, rectifier and controlcircuit which may be used to provide power and logic signals to theannunciator of FIG. 1;

FIG. 3 is a block diagram indicating the logic functions of the staticelements of FIG. 1 as connected to an indicator and an alarm;

FIG. 4 is a block diagram of a second embodiment of the invention;

PEG. 5 is a block diagram of a third embodiment of the invention;

FIG. 6 is a block diagram of a fourth embodiment of the invention;

FIG. 7 is a block diagram of a fifth embodiment of the invention; and

FIG. 8 is a schematic diagram of a static flasher comprised of staticelements.

The annunciator systems in this application are illustrated by usingstatic elements which include diodes and a plurality of saturable corestatic logic elements, which are different from each other in detailedstructure, to provide different ones of the logic functions AND, OR, NOTand NOT-MEMORY. The various logic elements thus constructed are combinedwith each other and with various indicator devices to compriseannunciator systems which respond to abnormal conditions at a monitoredpoint. The monitor may be a conventional trouble sensing device of thebinary type such as a pressure switch, ratio switch, temperature switch,a limit switch of the magnetic or contact type, or a proximity switch,any one of which may open or close a contact in response to abnormalvariations at the monitored point. Thus, the annunciator respondsdirectly to the presence of a normally absent signal or to the absenceof a normally present signal.

The following description is divided into two major parts. The firstpart is directed to the structure and operation of the different ones ofthe individual static saturable core logic elements. The second part isdirected to the manner in which the logic elements may be interconnectedwith each other and combined with various indicator devices to performthe different annunciator functions in annunciator systems embodyingthis invention.

STATIC LOGIC ELEMENTS The logic elements used in the annunciatorsdisclosed are of the static type, since they give important advantagesover the relays used in prior annunciators. The static logic elementsshown and described herein are made up of all static parts such asdiodes, magnetic cores and resistors. While these particular elements,and the specific arrangements thereof, are an important part of thespecific aspects of the invention; it is to be understood that thebroader aspects of the invention may be utilized through the use ofother arrangements of these and/or other static parts.

The use of such static logic or decision elements gives many advantagessuch as: (1) there are no moving parts to wear and be replaced, (2)there are no contacts in the annunciator units to burn, stick or becomedirty and fail to operate, (3) the power consumption is small, (4)operation is extremely fast with momentary application of a signal foras short a time as one cycle giving the required operation of thesystem, and (5) the annunciator is reliable in operation and requiressubstantially no maintenance.

Diflerent nomenclature may be used for the various static logic ordecision elements and their functions as used in the invention, and thenames which have been chosen for use herein are as set forth below.

In the AND function, an output is obtained only when all of a givennumber of input signals are applied.

In the OR function, an output is obtained when any one of a number ofinputs is applied.

In the NOT function, an output can be obtained only when no input signalis applied.

In the MEMORY function, sometimes called a FLIP- FLOP, an output occursin response to an input, which output remains after termination of theinput until the occurrence of a condition other than the change of the,9 input condition. A NOT-MEMORY is a memory comprised of a plurality ofstatic NOT elements.

FIG. 1 of the drawing is directed to the body of one unit of anannunciator system embodying this invention for monitoring one point andincludes schematic diagrams of typical OR elements OR 71 and OR '73, aNOT element N10, a two-input AND element All, a NOT- MEMORY element NM12and a two-input AND amplifier A13. Power is supplied to these elementsfrom the power supply unit of FIG. 2.

The individual logic or decision elements will first be described,together with certain interconnections with each other and with thepower supply unit, since an understanding of these elements willfacilitate an understanding of the complete annunciator systemsdescribed in the second part hereof.

In FIG. 1 of the drawing, each terminal reference numeral ending in agiven letter is connected to the output terminal of the power supplyunit of FIG. 2 having a reference numeral ending in the same letter.

The two-input AND element All is comprised of a central saturable core14 having a gate winding 15 and a reset winding 16. The reset circuitmay be traced from terminal 52A, which is supplied with power fromterminal 17A of the transformer (FIG. 2), through winding 16, rectifier18, terminal 37, rectifier 19, input conductors 2t 21, 22 and 23,terminal 38, rectifier 24 to common 25B, common 26B (FIG. 2) andterminal 27B of the transformer. If this switching element All were asingle input AND, no other reset circuit would be provided; however,another input conductor 30 of the two-input AND provides a secondpossible reset circuit for the reset current for winding 16. This secondreset circuit may be traced from terminal 52A through winding 16, butnow deviates through rectifier 28, terminal 39, rectifier 29, conductor30 and input terminal 19512. An inputsignal may be applied to inputterminal 195L by a connection from terminal 196L (FIG. 2) rectifier 1W7,rectifier 198 to common 199B.

The above-described apparent current flow in a reverse direction throughrectifiers 19 and 24, for example, may

occur because of the high voltage negative bias circuit throughtransformer terminals 27B, 26B, common 25B, rectifier 24, terminal 38,conductors 23, 22, 21 and 20, rectifier 19, terminal 37, resistor 40,terminal 41C,

transformer terminals 42C and 43C. The negative bias current ismaintained at a low level by resistor 40 but is always larger than thereset exciting current. Accordingly, the net current flow throughrectifiers 24 and 19 is always in the forward direction. Thus,rectifiers 24 and 19 are forward biased rectifiers and therefore common258 is'always slightly positive with respect to terminal 37. As long asreset current doesnot exceed the current in the negative bias circuit,the principle of superposition is applicable in the same manner as itapplies in known manner to a bilateral resistor. Accordingly, the resetcurrent can in effect flow through rectifiers l9 and 24 in the reversedirection to accomplish reset of the core in the manner set forth above.

The above-identified high voltage negative bias circuit is alsoidentified as a non-linear resistance circuit be- 7 cause the rectifiersl9 and 24 are reverse biased when a is applied through conductor 30.When such voltages are applied during a reset half cycle, terminal 37and 39 are more positive than common and thus block the reset excitingcurrent. The rectifier 2a is thus reverse biased. At the same time, thepotential difference between input voltages, the reset supply voltageand the negative bias passes a current through resistors 40 and 52.Reference is made to the copending application of Harley A. Perkins,Jr., Serial No. 640,006, filed Febru ary 13, 1957, which issued June 19,1962 as US. Patent 3,040,242, for further explanation of the structureand operation of this non-linear resistance circuit.

The gating circuit for the AND element All may be traced from windingterminal 46D, which is energized from transformer terminal 45D, throughwinding15, rectifiers 47 and 4S, and common 49B and transformer common263 to transformer terminal 273. Rectifier 48 is the non-linear elementfor the gate winding and is structurally and operationally the same asthe hereinbefore'discussed non-linear devices. This non-linearresistance circuit may be traced from transformer terminal 27B, common26B, common 49B, rectifier 48, resistance 56, terminal 51B andtransformer terminals 52E and 53B.

When no input is presentin either one of conductors 30 or 2%, the core14 traverses through its rectangular hysteresis loop each cycle. Thepreviously described gating circuit drives the core 14 toward positivesaturation when the gate voltage goes positive, the gate voltage being asine wave. At the same time, the non-linear resistance circuit voltageacross resistor St is going negative to cause a current to flow in theforward direction through rectifier 43 in the manner hereinbeforedescribed. During the following half-cycle of the gate voltage, therectifier 47 blocks the current flow attempting to drive the coretowards negative saturation. At this time, the reset voltage, also asine wave, is positive and drives the core toward negative saturation inthe manner hereinbefore discussed. Simultaneously the nonlinear circuitvoltage across resistors 40 and 52 is going negative causing a currentto flow in the forward direction through the non-linear resistancecircuits. Thus, the core alternates between positive and negativesaturation.

FIG. 2 is a schematic diagram of the power supply or transformercircuit, referred to in part in the above description of the reset andgating circuits, which may be used to provide the hereinbefore mentionedout-of-phase relationship between the gate voltage and the resetvoltage, and also provide the in-phase relationships between each ofthese voltages and its attending negative bias circuit. An alternatingcurrent source 53 is suitably connected to the primary winding 54. Thesecondary winding 55 is provided with seven taps, namely, end taps 53Band 43C, center tap 27B and intermediate taps 56F, 17A, 57G and 45D.Center tap 27B is used as common. When the 45D tap of the transformer isin the positive going half cycle of its full wave cycle with respect tocommon, said tap providing the gate voltage for winding 15, tap 17A isin its negative going half cycle of its full wave cycle with respect tocommon, said tap providing the reset voltage for winding 16., Similarly,the 43C tap acting in series with rectifier C provides a half-waverectified negative bias for the non-linear element 48 in phase with thegate supply tap 45D while the 535 tap acting in series with rectifier Eprovides a half wave rectified negative bias for the nonlinear elementsin the reset circuit of the AND element All and in, phase with the resetvoltage from terminal It is obvious that the taps may be positioned toto centertap 273. To clarify the hereinbefore described phaserelationships, the symbol 0 indicates all points which have the samephase relationship at any instant while the symbol at represents allpoints which are 180 out of phase with the points 0 at the same instant.

It is desirable that a plurality of these logic circuits be arranged sothat the output of one provides the input for another. Such constructionnecessitates an iii-phase connected to each other at terminal '76.

e) relationship between the gating circuit of the driving saturable coredevice and the reset circuit of the driven saturable core device toprovide the previously discussed blocking action. The intermediate tap56F is a gate supply voltage 180 out-of-phase With gate voltage supplytap 45D to provide opposed phase taps, to be selected at will, forproper connection for accomplishing this type of phasing relationship.Similarly, intermediate tap 57G is a reset voltage 180 out of phase withreset voltage supply tap lllA. The use of these additional taps in thisrespect for proper phasing between static elements will become apparentin the description of the annunciator systems hereinafter set forth;

in the two-input AND circuit All described hereinbefore, an output isproduced by preventing reset of the core by blocking rectifiers 23 and13 'm the reset circuit thereof. This is done by feeding in a signal ofthe same phase and of greater amplitude than the reset voltage, throughrectifiers l9 and 29. In this instance, 15 volts, the value of the gatesupply voltage, is suitable as a blocking voltage. This blocking voltageprevents the reset voltage from accomplishing reset. Since the core 14is thus already at positive saturation, it cannot support any positivevoltage and will, therefore, gate an output when the gate voltage goespositive on the next half cycle. If either one of the rectifiers 18 or28 are not blocked, reset of the core 14 can occur therethrough and nooutput will appear.

The two-input AND amplifier A13 is operationally identical with thehereinbefore described two-input AND circuit All. Structurally, the ANDelement and the amplifier differ only in respect to minor changes suchas the number of windings on the saturable core which can be changed toprovide a higher output power. Other changes in structure and materialto provide a higher power output will be obvious to one skilled in theart.

The two-input AND amplifier A15 is comprised of a saturable core 5%, areset winding 57 and a gate Winding 58. The reset circuit may be tracedfrom transformer 57G, reset terminal 536, winding 57, rectifiers 58, 59and dil, conductor till, terminals 62 and 63, non-linear element 48, tocommon 49B and transformer terminals and 2719. It may be noted that thiscircuitry provides for in-phase operation with respect to the gatecircuit of AND element All serving as the driving circuit or inputcircuit through conductor 61 to the amplifier A33. The negative biascircuit for the reset circuit may be traced from transformer terminal273, common 263, common 43B, rectifier or non-linear element 43,conductor 64-, terminal 62, conductor 61, rectifiers 6i) and 59,terminal 65, resistor 66, terminals to and 66B and transformer terminals52B and SEE.

Rectifiers 60 and 69 are connected at terminal 7i? so that either one orboth may provide an output through rectifier 59 to block the resetvoltage through rectifier 58. Accordingly, rectifiers dd, 69 andterminal "ill comprise an OR element 01171 which in turn constitutes oneinput of the two-input AND amplifier A13. The other input of the ANDamplifier Alli-l is provided through rectifier 72, which in turn isconnected to the output of an output of an OR element OR'73 having aninput through either of rectifier 7 or rectifier 75, which are Thus, analternate reset circuit for Winding 5'7 may be traced from transformerterminal 576, winding terminal 586, Winding 57, terminal 77, rectifiers78, 72 and 74-, terminal '79, conductor terminal fil, conductors 23, 22and 21, terminal 32-, conductor 83, terminal 84, rectifier $5, to common86B and transformer common 26B and terminal 278. The negative biascircuit may be traced from common 863 back through the previously tracedreset traced reset circuit to rectifier 72, terminal $7, resistor 8%,terminals 67 and dtlE to transformer terminals 52E and 53E.

The gate circuit of the amplifier A13 may be traced from transformerterminal 56?, winding terminal 8%, winding 5%, rectifier sea, terminal3%, non-linear element 61, to common 62B, and transformer common 26B andterminal 273. The negative bias circuit may be traced from transformerterminals 27B and common 263 to common 62B, non-linear element 61,terminal 60, resistor 89, terminal 9iiC and transformer terminals 42Cand 43C.

The NOT circuit Nlil differs from the two-input AND circuit All in thatit has only one input and no reset supply voltage is provided for thecore 91. The core )1 is then generally at positive saturation and anoutput occurs through terminal Q4 and conductor for each gatinghalf-cycle. When an input is present through conductor 31 and rectifier32, reset of core 91 occurs th ough terminal 96, reset winding 9'7,terminal 93, and the non-linear resistance circuit comprised of terminal99E, resistance fill), non-linear element Till and common NE. T henon-linear resistance circuit is connected appropriately acrosstransformer common 26B and negative bias terminal 52E. The gatingcircuit may be traced from transformer terminal 56F, terminal 3F, gatewinding @3, rectifier 1%, terminal $4, non-linear element 35 and commonto transformer common 265. The non-linear resistance circuit may betraced from trans former common 268, common 36B, non-linear element 35',terminal 94, resistor lltid, terminal 295 to transformer terminals 42Cand In this NOT circuit Nftl, conductor 33 and rectifier 34 areineffective and are included only because such structure becomes usefulwhen two such NOT circuits are interconnected to form a NOT-It ZEMORY asat element NMTZ as hereinafter described.

The NOT-MEMORY circuit MMTZ is comprised of two NOT circuits Nl'ZH andNTZK, each identical in structure and operation to the NOT circuit Nltl'as hereinbefore described. The NOT circuit NTZH includes a core 1%, aninput reset winding N7 and a gate winding Ttlfi. The input-reset circuitmay be traced from positive input terrmnal ill, reset winding 167, thento a non-linear resistance circuit comprising a non-linear element 112and resistor $.13 connected through common 114B and terminal 115C to thetransformer common 26B and terminal 42C respectively. The gate circuitmay be traced from transformer terminal 452), gate terminal lid, gateWinding 163, rectifier 1T7, terminal 84, to common 863 through nondinearelement 85. The non-linear resistance circuit also includes resistorill-.3 connected to terminal llli E, and transformer terminal 52E. Whenno input signal is present at terminal ill to actuate reset coil 167, anoutput is gated to conductor 83.

The other NOT circuit NTZK includes a saturable core 120, an input-resetWinding 122i and a gate winding 44. The input-reset circuit may betraced through positive input terminal 122, reset winding 121, then tocommon 12433 through non-linear element 123. The non-linear resistancecircuit may be traced from transformer common 26B, and common throughnon-linear element 123, resistor 125 to terminal 126E and transformerterminal 52E. The gate circuit maybe traced from transformer terminal56F to gate terminal 127R gate Winding 44, rectifier 128, terminal 38,non-linear element 24 to common 25B and transformer common 263. Thenon-linear resistance circuit maybe traced from common 25B, non-linearelement 24, terminal 3%, resistor T29, terminal 139C to transformerterminal When no input signal is present at terminal 122; to actuatereset winding 121, an output is gated through gate winding 44, rectifier128, and terminal 38 to conductor 131.

The NOT circuits N 12H and N121; are interconnected to form theNOT-MEMORY circuit NMlZ. The output of each NOT circuit is connected tothe input of the other. Thus, output conductor 13}. of NOT circuit N12Kis connected to input terminal 111 of NOT circuit NlZH through terminal81, conductor 23, terminal 132, conprised of rectifiers 137 and 1 2iRectifiers M and 11-39 are connected to inputs external of theNOT-MEMORY system.

In the operation of the NOT-MEMORY circuit, if no input signal ispresent through rectifier lid to the reset winding 107, core 106 is notreset and thus a half-cycle later the gate circuit including winding M28gates an output through the conductors 83, 21, 22, 23 and 13s torectifier 137 and reset winding 121 of NOT circuit NllZK to thus resetcore 120. A half-cycle later, the gate circuit of NOT circuit NTZKincluding winding 44 does not gate an output through rectifier 128, andconductors 131, "23, 22, and 134. Thus NOT circuit NIZH has no input andtherefore has an output to again reset core 121 in NOT circuit NlZK.This stable condition is therefore selfsustaining. The output is ahalf-wave voltage in phase with the gate voltage to winding of NOTcircuit NTZH. This output appears external-1y of the NOT-MEMORY circuitthrough terminal 82 to conductor 20, and through terminal 81, toconductors 3t 1% and T47. If an input voltage is now applied throughrectifier 116 to reset winding 107 of NOT circuit NIZH, core 1% willreset. A half-cycle later no output appears from NOT circuit NllZHacross conductors 83, 21, 22. and 136 to the inputreset Winding of NOTcircuit NTZK and thus core 12% is not reset. A half-cycle later, NOTcircuit NlZK gates a second output through winding 44 and rectifier 12%to conductor 131, which second output is opposite in phase to the firstoutput. The second output appears externally of the NOT-MEMORY circuitthrough terminal 81 to conductors 8t and 141, and through conductors 23,22 and 21 to terminal 82 and then to external conductor 20. This secondoutput also resets core 106 of NOT circuit N12H through conductors 131,23, 2.2, 134, rectifier 135 and input-reset winding 1657 so that NOTcircuit NdZI-l will have no output on its gating half-cycle. Even thoughthe input is removed, the output remains stably in this condition. Theoutput may be shifted back to the original phase'by presenting an inputvoltage to NOT circuit NlZK through conductor 142 and rectifier 1% ofthe OR element OR139. It is to be noted that normally the NOT- MEMORYhas an output of either one phase or the other. However, only one ofthese outputswill be eitective with respect to any other static elementto be driven thereby.

ANNUNCIATOR SYSTEMS The plurality of saturable core switching deviceshereinbefore described are interconnected with each other and combinedwith various indicator devices to comprise annunciators embodying thisinvention as shown in FIGS. 3 through 7. Each of these annunciators tobe described hereinafter is comprised of an alarm or audible indicatorsystem, a light or visual indicator system and an acknowledge system.These individual systems difier in detail firorn one annunciator toanother, but the basic cooperation between systems is common to alldisclosed annunciators and follows the operation pattern of Chart l.

Normal states 1 and 4 are the same thus indicating that the annunciatorsystem returns to normal when the sensing device return to normal.Accordingly, the annunciator system may go directly irom state 2 tostate 4, omitting state 3, when the abnormal condition is correctedbefore the acknowledge signal is provided.

In addition to the primary function of the annunciator to actuate analarm and visual indicators, it may be desirable that other signals begenerated that can be used in another control system to cause automaticshutdown or corrective procedure. These features will be more fullyexplained hereinafter.

FIG. 1 discloses one mode of interconnecting the various static logicelements to provide the annunciator functions set forth in Chart 1. PEG.3 is a symbolic diagram of the system of FIG. 1 showing the sameinterconnections between the logic elements, but showing the logicelements in symbolic form, and additionally showing the variousindicator devices combined therewith to provide the dusired annunciatorsignals.

The annunciator system of FIG. 1 and FIG. 3 is constructed to respond toan abnormal condition as indicated by the presence of a normally absentsignal and may be driven by direct current or full wave rectified directcurrent of a proper voltage and phasing to provide a proper input forthe static logic circuits hereinbefore described.

Referring to FIG. 3, the output through normally open contact 143 of atrouble sensing device (not'shown) is connected to the input of NOTelement N10 through conductor 31 which contact when closed provides NOTelement N16 with a signal from terminal 1%L of transformer-rectifierdirect current source 2% (shown in detail in FIG. 2 The output ofterminal .1961. is also connected at terminal 1951. to one input of ANDelement Alli through conductor 34 The output of NOT element N10 isconnected to a conductor 146 providing a signal to other equipment (notshown) when a signal from the sensing device is not present, and couldbe used to automatically start or stop such other equipment as may bedesired. The output'of NOT element Nlltl also is connected to one inputof NOT-MEMORY element NMlZ through conductor 95. An acknowledge switch144 is connected to the other inputof NOT-MEMORY element NMTZ throughconductor 1.42, which switch when closed provides NOT-MEMORY elementNMTZ with a signal from terminal 292 of transformer-rectifier directcurrent source 2M (FIG. 2). One output of the NOT-MEMORY element NMlZ isconnected to the other input of AND element All through conductor 26.The AND element Ali output is connected through conductors 6d and 21.45and through OR element'ORlfid to drive a horn amplifier'and a horn. TheA11 output is also connected to one input of OR element 01171 throughconductors 6d and 61. The second output of the NOT-MEMORY element NMlZis connected to a shut down element (not shown) for other equipmentthrough conductors 141 The second NOT-MEMORY output is also connectedfirst to Y the second input of OR element OR71 through conductors 8t and147 and, second, to the first input of OR element ORIS throughconductors 8d and M8. The second input Zltl of OR element 01173 isconnected to the output from flasher unit 221 for providing an output tothe other input of the AND amplifier A13 through conductor 158. The ANDamplifier A13 output is connected to actuate an indicator such as a lampL through conductor 1521. The lamp is connected in series circuitrelationship with a resistor arouses 152. A suitable direct currentsource of power, such as may be supplied by taps 45D and 5635 of thetransformer of FIG. 2 through rectifiers 2&3 and 2% respectively, isconnected to resistor T52 and across the lamp to common to provide thedimly lit visual signal of the normal state hereinbefore described. Itis obvious that the voltage value and resistor value may be adjusted toprovide any desired degree of contrast between the dimly lit conditionand the steady bright condition. The normal dimly lit condition of thelamps eliminates the necessity of periodically testing the lamps.

When an abnormal condition occurs at the monitored point in theannunciator of FIG. 3, contact 143 closes to provide a signal of propervoltage and phase to the input of the annunciator. A practical voltageof 15 volts may be provided through a step-down transformer andrectifier 2953 (FIG. 2) having a primary coil energized by thealternating current source 53 of PEG. 2. This signal provides an inputto NOT element Nit) which then gates no output to the NOT-MEMORY elementNMTTZ. The removal of the NOT-MEMORY input in this manner does noteflect its output because of the hereinbefore described memory featureand accordingly the NOT-MEMORY continues to gate an output of properphase to one input of the AND element All. The closed contact 143 alsoprovides an input signal to the other input of the AND element All.Thus, the AND element All gates an output to sound the horn. The ANDoutput also drives an input or" the two-input AND amplifier A13 throughthe OR element OR71. The flasher 221 provides a periodic output to theother input of the two-input AND amplifier A13 through the OR elementOR73. The last two mentioned inputs cooperate to provide a periodicoutput from the AND amplifier A13 to flash the light.

It is a very desirable feature of the invention that the flasher 211 isconnected into the circuit of the lamp on the input side of theamplifier A13. This makes it possible to use a flasher of low-energyoutput, which is small and compact and still use a single flasher forsupplying a substantial number of annunciator points as is describedhereinafter. This advantageous result is obtained because the flasherdoes not have to supply the energy for lighting the lamps, since thisenergy is supplied to the amplifier A13 (referring to FIG. 1) at theterminal 8? of the gate winding 53, from the terminal 56E of the powersupply unit, shown in FIG. 2. There is further advantage in the use of aflasher composed of static elements, as shown in FIG. 8, since there areno moving parts to wear or stick, and there are no contacts or movingcommutators, which are likely to wear and burn due to arcing,particularly if the flasher has to interrupt the power required to lightthe lamp or lamps.

These advantages of the flasher arrangement are illustrated byconsidering, for example, one practical embodiment of the inventionwhere each lamp requires 350 milliamperes at 4 volts half-Wave directcurrent, so that the flasher would have to handle 3500 milliamperes, if10 lamps might be lighted simultaneously and flashed directly by theflasher. By having the flasher connected at the input side of the ANDamplifier A13, the current required of the flasher for each point isonly 6 ma; or 60 ma. if the lights at ten points might have to beflashed, compared With the current of 3500 ma. which would otherwise berequired for the ten points. This makes possible the use of a small lowcost flasher which uses only static parts. By providing an individualAND amplifier A13 for the light for each point, each amplifier need havean output of only 350 ma. and may also be of low-cost static parts andof the type which is frequently used as a preamplifier at the input of alarger amplifier; which is not required in the lamp circuits of thearrangements described herein.

If, when the audio alarm is sounded and the light is flashing, theoperator temporarily closes the acknowledge switch 144, an input signalis provided to the other terminal of the NOT-MEMORY element Nit/{i2causing it to gate an output having a phase opposite to that of itsfirst mentioned output. This change in output phasing is equivalent tono input for the one input of the AND element All since the drivingvoltage from the NOT- MEMORY and the reset voltage of the AND elementare no longer in phase. Thus, the AND element All gates no output andthe horn is silenced. The aforementioned change in NOT-MEMORY outputphasing now provides a driving input for the AND amplifier A313 throughOR71 and also through 01173 to provide both inputs of the AND amplifierA13 with a steady signal. Accordingly, the AND amplifier A13 gates acontinuous output which causes the lamp to assume a steady brightcondition.

When the abnormal condition is eliminated, contact 143 opens toterminate an input signal to the AND element All and to the NOT elementN19. The NOT element Nld thus gates an output to the first mentioned NOT-AEMORY input causing the NOT-MEMORY output to reassume its initialphasing to provide a driving input for one input of the AND element A11.The same phase change occurs simultaneously in the NOT-MEM- ORY outputleading to the AND amplifier A13; however, this output is nowout-of-phase with the AND amplifier reset voltage and thus effectivelyconstitutes no input for the AND amplifier The AND amplifier A13 gatesno output to thus terminate an output to the light. The lamp L now glowsdimly in the circuit including resistor 152.

It is obvious that if the abnormal condition is terminated before theacknowledge switch is closed, the signal to the one input of the ANDelement A11 is interrupted, thus terminating the AND output to silencethe horn and also to terminate the input through 01271 to the ANDamplifier A35 to thus permit the lamp to glow dimly again.

Thus far there has been described an annunciator for monitoring a singlepoint to indicate a change in cond tion indicated by closing of theswitch 143, and it will he understood that in most annunciator systemsthere will be a plurality of monitored points indicated in FIG. 3 by theadditional switches K43 and 143". There will then be connected to eachadditional input terminal ESL and 1.951, a duplicate of the circuitpreviously described (indicated by the box or dot da h lines) eachincluding the elements Nil All, NMliZ, ORYll, ORTS, A13 and lamp L. Thusit may be determined from the lighting of one or more of the pluralityof lamps L, L and L" which of the respective signal initiating devices143, 16-5 and 143" has been actuated.

How-lever, there need be only one audible alarm such as a horn hell orbuzzer common to all of the monitored points. This one alarm and itsassociated amplifier is connected to the circuit for each monitoredpoint through the common OR element 011154 which has as many inputs M5,M5 and 1.45 as there are monitored points, so that the actuation of anysignal initiation switch lid-3, 1 3 or 14-3" will cause the one audiblealarm to sound.

As previously pointed out there may be only one flasher unit common toall or a group of the monitored points, since it is connected through aflasher bus 212 to the flasher inputs 21d, 23d and 21d of the respectivecircuits for the dilierent points. Furthermore, there is only a singleacknowledge or audio silence switch 144 for all, or a group of themonitored points. Conductor provides for connecting the single audiosilence switch 144 in common with all such plural annunciators. itshould be noted that closing the switch 144 when the system is in anormal condition has no effect since both inputs to the NOT-MEMORY wouldthus be provided with signals to reset both NOT elements of the NOT-MEMORY, in which event there arises a no-output condition.

In FIGS. 4 through 7 there are disclosed block diagrams of modifiedannunciators. For purposes of simplification, each system is shown asmonitoring a single point, but it will be understood that the equipmentindividual to each point will be duplicated for other points and that asingle horn circuit, a single flasher and a single reset oracknowledgement switch may be used in common to all, or a group, of themonitored points, as shown and described in detail in connection withPEG. 3.

Referring now to FIG. 4, there is disclosed a symbolic diagram of anannunciator having static logic elements of the same type as disclosedin FIG. 1. The static logic elements are interconnected in a differentfashion but cooperate to perform the same functions as that of the FIG.1 annunciator. In addition, the annunciator of FIG. 4 differs from thatof FTGS. l and 3 in that it is adapted to respond to the absence of anormally present signal. It will be obvious to one skilled in the arthow the static logic elements of the type shown in FIG. 1 may beinterconnected in the manner illustrated in PEG. 4 and described in thefollowing matter relating thereto.

In the annunciator systemof FIG. 4, a trouble sensing device (not shown)operates to open normally closed contact 156 to terminate the inputsignal to NOT element N157 through the OR element 011158, thus causingNOT element N157 to gate an output to the horn ampliher and horn to thussound the audio indicator. The NOT element N157 output also drives atwo-input AND element A159 in cooperation with the flasher outputprovided at the other input of the AND element AND A159. AND amplifierA161) then gates a periodic output to change the lamp signal from asteady dim condition to a flashing bright condition. The termination ofthe input .to the NOT-MEMORY element NM161 has no effect upon itsoutput, therefore, it continues to effectively gate no output withrespect to the NOT element NOT N157 and the AND amplifier 161). If theoperator now closes acknowledge switch 162, NOT-MEMORY element Nit 1161gates an effective output through the OR element O'R158 to cause the NOTelement NOT N157 to terminate its output to the audio system thussilencing the horn. At the same time, the NOT-MEMORY element Nit i161output changes the lamp condition from one of flashing bright to one ofsteady bright through the OR element OR164- and amplifier A166.Elimination of the abnormal condition closes the contact 156 to restorean input signal to the NOT-MEMORY element NM161 and the NOT elementN157. The NOT-MEMORY element NM161 then returns to its previouscondition of no effectwo output thus eliminating an input to thepreamplifier A169 and permitting the lamp to return to its steady dimcondition in its circuit including resistor 163. NOT element N157 thengates no output and thus permits the audio signal to remain in asilenced condition. At the same time, the no output condition of NOTelement N157 provides no input at one terminal of the AND element A159,thus prohibiting AND element 159 from gating an output to drivepreamplifier A166. The light remains in a dim condition. Conductorprovides a shutdown signal, if desired.

The acknowledge switch 162 and the audio indicator may be connected incommon with a plurality of annunciators in the same manner as disclosedin FIG. 3. It is obvious that if an abnormal condition is eliminatedbefore the acknowledge switch is closed, the hereinbefore d scribedoperations of the static logic element causing a change in signal fromsteady dim to flashing bright are reversed and the annunciator againassumes a normal condition.

Referring now to FIG. 5, there is disclosed in block diagram, a furtherembodiment of the invention in an annunciator having the same type ofstatic logic elements described in detail with respect to FIG. 1. Thelogic elements are interconnected in a manner not hereinbeforedescribed, but cooperate with each other to perform the same annunciatorfunctions as the foregoing annunciator systems. This annunciatorresponds to an abnormal conglows dimly in its circuit including resistor174.

12 dition as indicated by the absence of a normally present signal.

In the nnnunciator system of FIG. 5, a trouble sensing device (notshown) operates to open a normally closed I contact to thus terminate aninput signal through the OR element OR166 to NOT element N167 thuscausing it to gate an output to actuate the horn amplifier and horn. NOTelement N167 also provides an input to AND element A168 which gates anoutput to one input of the two-input AND preamplifier A169. through theOR clement OR17t). The flasher provides a periodic input to the otherinput of the AND preamplifier A169 through the OR element OR171 whichcooperates with the first mentioned AND preamplifier input to cause thepreamplifier to gate an output to periodically energize the lamp to thusprovide the flashing bright condition. The absence of the normallypresent annunoiator input signal has no effect on the N OT-MEMORYelement NM172 which continues to gate an ineffective output with respectto NOT element N167. If the operator now closes acknowledge switch 173,NOT-MEMORY element NM172 now is actuated to its opposite gatingcondition and now gates an effective output to NOT element N167 causingit to gate no output to thus terminate the signal to one input of theAND amplifier A169. The lack of a NOT element N167 output likewiseterminates the signal to the audio signal system thus silencing thehorn. The same NOT- MEMORY output also now provides a steady effectivesignal to both inputs of the AND amplifier A169 through each of theelements 011176 and OR1'71. AND amplifier 169 now gates at steady outputcausing the lamp to assume a steady bright condition. Elimination of theabnormal condition causes the sensing device to recl'ose switch 165, inwhich event an input signal is reapplied to the opposite terminal ofNOT-MEMORY element NM172 reversing its output condition thus producingan ineffective output with respect to NOT element N167 and with respectto the two inputs of amplifier A169. The reclosed switch also providesan input through the OR element OR166 to NOT element N167 which nowgates no output to either audio or visual signal, The lamp now If theabnormal condition should be corrected before the acknowledge switch isclosed, it is obvious that the hereinbefore described operations of thestatic logic elements causing a change from a dimly glowing visualcondition to a flashing bright condition combined with sounding audioalarm are reversed. Conductor 205 provides a shutdown signal if desired.

The indicator silence switch 1'73 and the audio system may be connectedin common with a plurality of annunciators in the same manner asdisclosed in FIG. 3.

eferring now to FIG. 6, there is disclosed in block diagram a furtherembodiment of the invention in an annunciator having the same type ofstatic logic elements described in detail with respect to FIG. 1. Thelogic elements are interconnected in a manner not hereinbeforedescribed, but cooperate with each other to perform the same annunciatorfunctions as the foregoing annunciator systems. This annunciatorresponds to an abnormal condition as indicated by the presence of anormally absent signal. In addition, the annunciator of FIG. 6 mayrespond to an annunciator input signal consisting of direct current,alternating current, one-half wave direct current or full wave directcurrent as desired- In the annuncia-tor system of FIG. 6, a troublesensing device (not shown) operates to close a normally open contact 175to provide an annunciator input signal in a first direction to NOTelement N176 and in a second direction through the OR element OR177 toone input of the two-input AND amplifier A178. As a result, NOT elementN176 ceases gating an output through the OR element 011179 to one of theplural inputs of AND element A195. The remaining two inputs of ANDelement A195, shown unconnected to other devices, lead 13 from theoutputs of similarly arranged OR elements in other annunciator systems(not shown) of the same type as the annunciator now described, whereinan abnormal condition at the monitored point provides a signal throughthe respective OR elements as through the OR element OR179 as abovedescribed. Conversely a normal condition will provide no signal throughthe OR element OR179. Therefore, when conditions at all monitored pointsare normal, AND element AllrS gates an output to NOT element Nlfiliwhich responds to gate no output to the horn amplifier to maintain thehorn in a silenced condition. An abnormal condition causes NOT elementN176 to gate no output causing AND element A195 to gate no output to NOTelement N130. NOT element N184) then gates an output to actuate the hornamplifier to sound the horn. It is seen that an abnormal condition atany monitored point terminates an output from AND element A195, commonto all annunciators, to sound the common audio indicator. Conductor 1%may be provided to lead directly to other annunciators to connect theaudio indicator silence switch in common with all annunciators. NOTelement N176 also ceases gating an output to NOT-MEMORY element NMlSl;however, the absence of an input signal to NOT-MEMORY element NM181 hasno effect on NOT-MEMORY element NM181 which continues to gate anineffective output to AND element A182 and to the two input terminals ofthe two-input AND amplifier A178 through the OR elements OR177 andOR183. The annunciator input signal provided through contact 175,provides an input signal to one input of the AND amplifier A178 throughthe OR element OR177, which input cooperates with the periodic input tothe other AND amplifier input provided by the flasher unit to cause theAND amplifier A173 to gate a periodic output causing previously dimlyglowing lamp to assume a flashing bright condition. If the operator nowcloses acknowledge switch 184, an input signal is provided at the otherinput of NOT-MEMORY element NMT-Sf which then reverses its outputcondition to now gate an eliective out- "put to both inputs of thetwo-input AND amplifier A178 through the OR elements OR177 and ORiidd toprovide a steady output which changes the lamp condition from flashingbright to steady bright. Simultaneously, NOT- MEMORY element NM181 gatesan effective output to AND element A182; which gates an output throughthe OR elements OR179 and and A195 to NOT element N180. NOT element N180now ceases to gate an output and thus the audio alarm is silenced. Whenthe abnormal condition is eliminated, contact 175 opens to terminate theinput signal to NOT element N176 which then gates an output through theOR element 012179 to provide an input for NOT element NlSti which inturn is prevented from gating an output to sound the audio system. Theoutput from NOT element N176 provides an input to the opposite input ofNOT-MEMORY element NMlSll which reverses its output condition to gate anineffective output with respect to AND amplifier Ai'i'S and AND elementA182. The termination of the annunciator input signal likewiseinterrupts the input through the OR element R1l77 to one input of theAND amplifier A178 thus preventing the AND amplifier from gating anoutput to the lamp signal system. If the abnormal condition should beeliminated before the acknowledge switch is closed, it is obvious thatthe operations of the static logic elements which change the conditionof the lamp from one of dim glow to one of flashing bright are reversed.Conductor 206 provides a shutdown signal, if desired.

Referring now to FIG. 7, there is disclosed in block diagram 21 furtherembodiment of the invention in an annunciator having the same type ofstatic logic elements described in detail with regard to FIG. 1. Thelogic elements are interconnected in a manner not hereinbeforedescribed, but cooperate with each other to perform the same annunciatorfunctions as the foregoing annunciator systems. This annunciatorresponds to an abnormal condition as indicated by the absence of anormally present signal. In addition, the annunciator of FIG. 7 respondsto either direct current or full-wave direct current provided throughcontact 185 of the trouble sensing device (not shown).

In the annunciator of FIG. 7, a trouble sensing device (not shown)responds to an abnormal condition to open normally closed contact 185 tothus terminate the annunciator input signal to one input of NOT-MEMORYelement NMlifie which is unaffected by the interruption of its inputsignal and therefore continues to gate an ineffective output. Theaforementioned termination of the annunciator input signal throughcontact 185 provides no input through the OR element ORltis to NOTelement N187 to cause NOT element N187 to thus gate an output whichactuates the horn amplifier and sounds the horn. The aforementionedtermination of the input signal through contact 185 performs a thirdaction in terminating the input through the OR element 03.189 to NOTelement Nlti thu causing NOT element NlQtB to gate an output through theOR element 011191 to provide an input to the one input AND amplifierA192 which gates an output to actuate the lamp. At the same time, theflasher is providing a periodic input to NOT element N199 which nowgates a periodic output through the OR element ORE to AND element A192.to cause the lamp condition to change from a steady dim condition to aflashing bright condition. If the operator now closes the acknowledgeswitch 193', an input is provided to the other terminal of NOT-MEMORYelement NMldo which causes it to now gate an eifective output in a firstdirection through the OR element (Bi-119i to AND element A332 causing anoutput which provides a steady bright lamp condition, and in a seconddirection through the OR element ORlLSi-B to provide an input for NOTelement N187 which then gates no output to thus deactuate the hornamplifier and silence the horn. When the abnormal condition iseliminated, the sensing device closes its contact 3185 which provides anannunciator input in a first direction to the other input of NOT-MEMORYelement NME o causing it to reverse its output condition to gate anineffective input with respect to AND element A192 amplifier to tend toterminate the steady bright lamp condition and with respect to NOTelement N187 tending to cause it to gate an output to sound the horn.The annunciator input takes a second direction through the OR elementOR139 to NOT element N causing NOT element N 1% to gate no outputthrough the OR element ORTEBT to AND element A192 thus permitting thelamp to return to its normal dim condition in its circuit includingresistor 194. The flasher is ineffective since NOT element N195 is nowprovided with a steady input. The annunciator input takes a thirddirection through the OR element ORESS to NOT element N137 causing ano-output condition to deactivate the horn amplifier and silence thehorn. If the abnormal condition should be eliminated before theacknowledge switch is closed, it is obvious that the operations of thestatic logic elements causing the lamp to change condition from dim toflashing bright and causing the audio system to change from a silencedcondition to an audible condition, are reversed to cause the annunciatorsystem to reassume a normal condition. Conductor 2&7 provides a shutdownsignal, if desired.

A plurality of annunciators of the type shown in FIG. 7 may be connectedin common with audio silence switch 1% and the audio indicator in thesame manner as disclosed in FIG. 6.

FLASHER The flasher 221 disclosed in FIG. 8 provides the pulsatingsignal to the lamp preamplifier in the manner herein before describedand is comprised of a static element oscillater stage 222 and a staticelement butler stage 223. The oscillator stage 222 is comprised of twostatic magnetic NOT elements N224 and N225 interconnected with eachother and a pair of resistor-capacitor circuits to provide regenerativefeedback to sustain oscillation. The buffer stage 223 is comprised oftwo static magnetic IN- HiBITED-NOT elements IN273 and IN275interconnected with each other and connected to the oscillator toprovide high output power, to isolate the oscillator from its load, andto provide a fast switching action.

In the oscillator stage 222, the first NOT element N224 is comprised ofa magnetic core 226 having a gating winding 227 which may be energizedfrom transformer terminal 56F (FIG. 2) which may be connected to flasherterminal 22% Ga, conductor 229, winding 27, rectifier rectifier 231 ofnon-linear impedance 232, common conductor 2335 and flasher terminal 234Ca which may be connected to transformer common terminal 263. Thenon-linear impedance includes transformer terminal 525, flasher terminal235 Gb, conductors 23-5 and 236.1 rectifier 237, rectifier 231,conductor 233, terminal 234 Ca, and transformer terminal 26B. Rectifier23th and nonlinear impedance 232 connect gate Winding 227 to outputterminal 24%. The NOT reset winding 22% is connected to a NOT inputterminal 238 in circuit with a rectifier 239, rectifier 241 ofnon-linear impedance 242, conductor 233, terminal 23401, and transformer263. Thus winding 228 is energized in response to a positive signalapplied to NOT input terminal 233. The non-linear impedance includestransformer terminal 268, flasher terminal 2346a, conductor 233,rectifier 241, resistor 311, conductor 229, flasher terminal 228 Ga andtransformer terminal 26B.

The NOT element N225 of oscillator 222 is comprised of a magnetic core312 having a gating winding 243 which may be energized from transformerterminal 55D, through flasher terminal 235Gb conductor 2%, winding 243,rectifier 22 i, rectifier 245 of non-linear impedance 246, commonconductor 233a, flasher terminal 234Ca and transformer terminal 26B. Thenon-linear impedance 246 includes transformer terminal 26B, flasherterminal ZIdCa, conductor 233a, rectifier 2 35, resistor 247, conductors229a and 229, flasher terminal 223Ga and transformer terminal 42C.Rectifier and impedance 246 connect gate Winding 24?: to output terminal253. The magnetic core 312 is also provided with a NOT reset winding 247connected to NOT input terminal 248, rectifier 249, rectifier 251 ofnon-linear impedance 25ft}, conductor 233a, flasher terminal 23401, andtransformer terminal 263. Thus reset Winding 247 is connected to respondto a positive input, applied at NOT input terminai 248. The non-linearimpedance25tt includes transformer terminal 26B, flasher terminal 235061, conductor 233a, rectifier 251, resistor 252, conductor 2%,terminal 235Gb and transformer terminal 45]).

The output terminal 2% of NOT element N224 is connected through acapacitor 254 to the NOT input 248 of NOT element N225. The capacitor254 is also connected in circuit with a resistor 255 annd rectifiers 256and 259 which complete a hereinafter described discharge circuit forcapacitor 254. Similarly, the output terminal 253 of NOT element N225 isconnected through a capacitor 257 to the NOT input 238 of NOT elementN222. Capacitor 257 is also connected in circuit with a resistor 258annd rectifiers 259 and 256 which complete a hereinafter describeddischarge circuit for capacitor 257. The output terminal 2% of NOTelement N224 and the output terminal 253 of NOT element 224 are eachconnected to an input of the buffer stage 223 in a manner hereinafterdescribed.

In the buffer stage 223, the first static INHIBITED- NOT element 1N273'is comprised of a magnetic core 269 having a gate winding 261 and areset winding 2h2. The gate winding 2551i. may be energized fromtranscases former terminal 45D, through flasher terminal 235Gb,conductors 236 and 236a, winding 2X1, rectifier 263, rectifier 264 ofnon-linear impedance 265', conductor 233, flasher terminal 234Ca totransformer terminal 263. The non-linear impedance 265 includestransformer terminal 26B, flasher terminal 2340a, conductor 233,rectitier 26 d, resistor 26s, conductor 229 flasher terminal 2286a andtransformer terminal 565. Rectifier'263 and non-linear impedance 265connect gate winding 261 to output terminal 267. Thereset winding isconnected to NOT input terminal 268 through rectifier 269, reset Winding262, INHlB-TT input terminal 27d, rectifier 2'71 of non-linear impedance272, conductor 23 3, flasher terminal ZS-tCa to transformer terminal268. The nonlinear impedance 272 includes transformer terminal 263,flasher terminal 23401, conductor 233, rectifier 271, resister 2'74,conductors 236a and 236, flasher terminal 235Gb and transformer terminal45D.

The other INHIBITED-NOT element IN275 is comprised of a magnetic core276, a gate winding 277 and a reset winding 278. The gate winding 277 isenergized from transformer terminal 56F, flasher terminal 228cm,conductors 229 and 22%, winding 277, rectifier 279, rectifier 28d ofnondinear impedance 281, conductor 233a, flasher terminal 234Ca, totransformer terminal 268. The non-linear impedance includes transformerterminal 263, flasher terminal 234Ca, conductor 233a, rectifier 239,resistor 282, conductor 236, flasher terminal 235 and transformerterminal 45D. The rectifier 279 and non-linear impedance 28?. connectgate winding 277 to output terminal 267. The reset winding 27% isconnected to NOT input terminal 268 through rectifier 283', and isconnected through INHIBIT input terminal 284, rectifier 285 ofnon-linear impedance 286, conductor 233a, and terminal 2340a totransformer terminal Ca. The non-linear impedance 286 includestransformer terminal 26B, flasher terminal 2340a, conductor 233a,rectifier 285, resistor 22%), conductors 229a and 229, flasher terminal223 and transformer terminal 5 6 F.

The output terminal 241 of the oscillator 222 is connected throughrectifier 287 to the INHIBIT input terminal 270 of the buffer stage 223.Similarly, the output terminal 253 of the oscillator 222 is connectedthrough rectifier 2% to the TNHIBIT input terminal of the buffer stage223.

In describing the operation of the flasher 221 as hereinbeforedescribed, it is assumed that as a prime condition, NOT element N224 isgating an output signal through output terminal 240 to NOT element N225to 257. Additionally, capacitor 257 may discharge through rectifier 256through the transformer windings connected across terminals 2288a and2346a. The NOT element N224 thus receives no effective input to resetits core 226 and accordingly continues to gate an output tocapacitor'254. As capacitor 254 continues to charge, it eventuallyblocks the reset signal to NOT input terminal 24a; and at the same timereduces its own charging rate. The termination of the NOT input to resetwinding 247 causes NOT element N225 to begin gating an output throughits output terminal 253' to begin charging capacitor 257 and to causereset of core 226 through NOT input terminal 233. The NOT element 222-noW ceases gating an output through 249, thus permitting chargedcapacitor 54 to discharge through terminal 243, rectifier 237, resistors237 and 2'74, conductors 236a and 236, rectifier 256 and resistor 255back to capacitor 254. Additionally, capacitor 254 may discharge throughrectifier 259 through terminals 228Ga and 235Gb connected across thetransformer. The NOT element N225 thus receives no effective input toreset its core and accordingly continues to gate an output to reset core226 of NOT element N224 and to continue charging capacitor 257. Ascapacitor 257 continues to charge, it eventually blocks the reset signalto NOT in put terminal 238 and at the same time reduces its own chargingrate. The NOT element N224 begins gating an output to begin a new cycleof operation and thus the NOT elements N224 and N225 cooperate toprovide the desired oscillations.

As the NOT element N224 is gating an output signal through terminal 24-0to charge its associated capacitor 254 and reset core 312 of NOT elementN225, all in the manner hereinbefore described, the output throughterminal 240 also is providing a signal through rectifier 287 to INHIBITterminal 270 of INHIBITED-NOT element IN27 3 in the buffer stage 223.This INHIBIT input voltage signal is the same phase and opposite indirection to the reset voltage across reset winding 262. This inputsignal 270 increases as capacitor 257 charges to prevent full reset ofcore 226. When the INHIBIT signal reaches a predetermined level reset ofcore 26% is blocked causing it to gate an output through terminal 265,267 and flasher output terminal 2%. The output signal from the IN-HIBITED-NOT element IN273 is provided through NOT input terminal 268 andrectifier 233 to reset winding 278 of INHIBITED-NOT element IN275 tothus reset core 276 which prevents gating winding 277 from gating anoutput through rectifier 279 to output terminal 267 and flasher output299. The INHIBITED-NOT element IN273 continues gating an output toflasher terminal 290 so long as the NOT element N224 of the oscillatorstage 222 is gating an output. While NOT element N224 is gating anoutput, capacitor 257 is discharging to provide a signal through outputterminal 253 and rectifier 288 to INHIBIT input terminal 284 in themanner previously described. But, the NOT input signal is not blocked,as the voltage level on the capacitor is too low at this time and thusthe capacitor 257 discharge signal to INHIBIT terminal 284 isinsufficient to inhibit INHIBITED-NOT element IN2'75. In a similarfashion, when NOT element N225 is gating an output signal to chargecapacitor 257 and reset the NOT element N224 in the manner previouslydescribed, the output signal from N225 through output terminal 253 isproviding an input signal through rectifier 288 to INHIBIT terminal 284of INHIBIT ED-NOT element IN275. This INHIBIT signal opposes the NOTsignal to reset winding 278, thus blocking reset of core 276 which thengates an output through rectifier 279, and output terminal 267 toflasher output terminal 2%. At the same time, the output from IN2'75provides a signal through NOT terminal 269 to reset winding 262 causingreset of core 260 to thus terminate its output signal to flasher outputterminal 290.

Thus, it is seen that the buffer stage 223 responds to oscillations ofthe oscillator stage 222 to alternately provide signals of oppositephase to the flasher output terminal 290. Accordingly, if the outputterminal 290 is connected to an input terminal of a static element suchas preamplifier A13 of FIG. 3 or any of the preamplifiers ashereinbefore described, the output signal from 2% will periodically bein phase with the reset voltage of said static element thus providing apulsing on input signal.

The above described static flasher is disclosed and claimed in copendingapplication Serial No. 706,688, filed January 2, 1958, by Donald H,Noreen et al. which is assigned to the same assignee as the presentapplication.

Inasmuch as the annunciator embodying the features of this invention iscomprised of static logic elements having no moving parts, theannunciator is highly reliable in operation and requires substantiallyno maintenance.

Since certain of the above-described features may be changed withoutdeparting from the spirit and scope of this invention, it is intendedthat all the matter contained in the above description and shown in theaccompanying drawings should be considered as illustrative only.

I claim as my invention:

1. In an annunciator: an indicator; a two input AND element foroperating the indicator; a first OR element having its output connectedto one input of the AND ele ment; a second two input OR element havingits output connected to the other input of said AND element; another twoinput AND element having its output connected to one input of the firstOR element; a source of a pulsating signal having its output connectedto one input of the second OR element; a MEMORY element having two in-'puts, a first output connected to one input of the said another ANDelement, and having another output connected to the other input of eachof the first OR element and the second OR element; a NOT element havingits output connected to one input of the MEMORY element; a normallyopened condition responsive switch for providing a signal to the otherinput of said another AND element and to the NOT element; andacknowledgment means including a normally opened switch operable toprovide a signal to the other input of the MEMORY element.

2. In an annunciator: an indicator; a single input AND element foroperating the indicator; a first two input OR element for providing asignal to the AND element; a two input AND element for providing asignal to one input of the first OR element; a source of apulsatingsignal for providing a signal to one input of the two input ANDelement; a NOT element for providing a signal to the other input of thetwo input AND element; a second OR element for providing a signal to theNOT element; a normally closed condition responsive means normallyproviding a signal to one input of the second OR element; a MEMORY meansfor providing a signal simultaneously to the other input of each of thefirst OR element and the second OR element and having one input forreceiving the condition signal and another input; and, acknowledgmentmeans including a normally opened switch for providing a signal to theother input of the MEMORY element.

3. In an annunciator: an indicator; a two input AND element forproviding a signal to the indicator; a first two input OR element forproviding a signal to one input of the AND amplifier; a second two inputOR element for providing a signal to the other input of the AND element;a source of a pulsating signal for providing a signal to one input ofthe first OR element; a single input AND element for providing a signalto one input of the second OR ele ment; a NOT element for providing asignal to the single input AND element; a third two input OR element forproviding a signal to the NOT element; a MEMORY element having twoinputs for providing a signal to one input of the third OR element andto one input of the first OR element; condition responsive meansincluding a normally closed switch for providing a signal to the otherinput of the third OR element and to one input of the MEMORY element,and having one input for receiving the condition responsive meanssignal; acknowledgment means including a normally opened switch forproviding a signal to the other input of the MEMORY element.

4. In an annunciator: an indicator; a two input AND element forproviding a signal to the indicator; a first two input OR element forproviding a signal to one input of the two input AND element; a secondtwo input OR element for providing a signal to the other input of thetwo input AND element; a source of a pulsating signal for providing asignal to one input of the first OR element; a condition responsivemeans including a normally opened switch for providing a signal to oneinput of the second OR element; a MEMORY element having two inputs forproviding a signal to the other input of each of the first and second ORelements in response to 19 receipt of a signal at one input of theMEMORY element; an acknowledgment means including a normally openedswitch and operable to provide a signal to said one input of the MEMORYelement; 3. NOT element for providing a signal to the other input of theMEMORY element and having its input responsive to the conditionresponsive means.

5. In an annunciator: an indicator; a single input AND for providing asignal to the indicator; a first two input OR element for providing asignal to the AND element; a NOT element for providing a signal to oneinput of the first OR element; a second tWo input OR element forproviding a signal to the NOT element; a source of a pulsating signalfor providing a signal to one input of the second OR element; a MEMORYelement having two inputs for providing a signal to the other input ofthe first OR element in response to a signal at one of its inputs;acknowledgment means including a normally opened 20 switch for providinga signal to one input of the MEMORY element; and a condition responsivemeans including a normally closed switch for providing a signalsimultaneously to the other input of the MEMORY element and the otherinput of the second OR element.

References Cited in the file of this patent UNITED STATES PATENTS2,625,595 Boddy Ian. 13, 1953 2,724,104 Wild Nov. 15, 1955 2,730,704Warren 'Ian. 10, 1956 2,751,578 Johannesson June 19, 1956 2,762,997Boddy Sept. 11, 1956 2,807,006 Collins eta-l. Sept. 17, 1957 2,824,295Zaruba Feb. 18, 1958 2,832,948 Derr et al. Apr. 29, 1958 2,858,528Diener Oct. 28, 1958 2,931,018 Tellefsen et a1 Mar. 29, 1960

1. IN AN ANNUNCIATOR: AN INDICATOR; A TWO INPUT AND ELEMENT FOROPERATING THE INDICATOR; A FIRST OR ELEMENT HAVING ITS OUTPUT CONNECTEDTO ONE INPUT OF THE AND ELEMENT; A SECOND TWO INPUT OR ELEMENT HAVINGITS OUTPUT CONNECTED TO THE OTHER INPUT OF SAID AND ELEMENT; ANOTHER TWOINPUT AND ELEMENT HAVING ITS OUTPUT CONNECTED TO ONE INPUT OF THE FIRSTOR ELEMENT; A SOURCE OF A PULSATING SIGNAL HAVING ITS OUTPUT CONNECTEDTO ONE INPUT OF THE SECOND OR ELEMENT; A MEMORY ELEMENT HAVING TWOINPUTS, A FIRST OUTPUT CONNECTED TO ONE INPUT OF THE SAID ANOTHER ANDELEMENT, AND HAVING ANOTHER OUTPUT CONNECTED TO THE OTHER INPUT OF EACHOF THE FIRST OR ELEMENT AND THE SECOND OR ELEMENT; A NOT ELEMENT HAVINGITS OUTPUT CONNECTED TO ONE INPUT OF THE MEMORY ELEMENT; A NORMALLYOPENED CONDITION RESPONSIVE SWITCH FOR PROVIDING A SIGNAL TO THE OTHERINPUT OF SAID ANOTHER AND ELEMENT AND TO THE NOT ELEMENT; ANDACKNOWLEDGEMENT MEANS INCLUDING A NORMALLY OPENED SWITCH OPERABLE TOPROVIDE A SIGNAL TO THE OTHER INPUT OF THE MEMORY ELEMENT.